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| Am29PDL129H Data Sheet RETIRED PRODUCT This product has been retired and is not available for designs. For new and current designs, S29PL129J supersedes Am29PDL129H and is the factory-recommended migration path. Please refer to the S29PL129J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 26842 Revision B Amendment +3 Issue Date November 2, 2005 THIS PAGE LEFT INTENTIONALLY BLANK. Am29PDL129H 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control and Dual Chip Enable Inputs This product has been retired and is not available for designs. For new and current designs, S29PL129J supersedes Am29PDL129H and is the factory-recommended migration path. Please refer to the S29PL129J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES 128 Mbit Page Mode device -- Page size of 8 words: Fast page read access from random locations within the page -- 45 mA active read current -- 15 mA program/erase current -- 1 A typical standby mode current Dual Chip Enable inputs -- Two CE# inputs control selection of each half of the memory space SOFTWARE FEATURES Software command-set compatible with JEDEC 42.4 standard -- Backward compatible with Am29F and Am29LV families Single power supply operation -- Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications CFI (Common Flash Interface) complaint -- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Simultaneous Read/Write Operation -- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency switching from write to read operations Erase Suspend / Erase Resume -- Suspends an erase operation to allow read or program operations in other sectors of same bank FlexBank Architecture -- 4 separate banks, with up to two simultaneous operations per device -- Bank 1A: 48 Mbit (32 Kw x 96) -- Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31) -- Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) -- Bank 2B: 48 Mbit (32 Kw x 96) Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion Enhanced VersatileI/O TM (VIO) Control -- Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin -- VIO options at 1.8 V and 3 V I/O Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data WP#/ACC (Write Protect/Acceleration) input -- At VIL, hardware level protection for the first and last two 4K word sectors. -- At VIH, allows removal of sector protection -- At VHH, provides accelerated programming in a factory setting SecSi TM (Secured Silicon) Sector region -- Up to 128 words accessible through a command sequence -- Up to 64 factory-locked words -- Up to 64 customer-lockable words Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level Both top and bottom boot blocks in one device Manufactured on 0.13 m process technology 20-year data retention at 125C Minimum 1 million erase cycle guarantee per sector Password Sector Protection -- A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password PERFORMANCE CHARACTERISTICS High Performance -- Page access times as fast as 20 ns -- Random access times as fast as 55 ns Package options -- 80-ball Fine-pitch BGA -- Multi Chip Packages (MCP) Power consumption (typical values at 10 MHz) Publication Number: 26842 Rev: B Amendment/ +3 Issue Date: November 2, 2005 GENERAL DESCRIPTION The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The device is offered in an 80-ball Finepitch BGA package, and various multi-chip packages. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 85 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE1#, CE2#), write enable (WE#) and output enable (OE#) controls. Dual Chip Enables allow access to two 64 Mbit partitions of the 128 Mbit memory space. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD's Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Chip Enable Configuration CE1# Control Bank 1A 48 Mbit (32 Kw x 96) Bank 1B 16 Mbit (4 Kw x 8 and 32 Kw x 31) CE2# Control Bank 2A 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 2B 48 Mbit (32 Kw x 96) Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V or 2.7 V to 3.3 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Note: The next-generation S29PL129J will have a different bank configuration, as follows: Chip Enable Configuration CE1# Control Bank 1A 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 1B 48 Mbit (32 Kw x 96) CE2# Control Bank 2A 48 Mbit (32 Kw x 96) Bank 2B 16 Mbit (4 Kw x 8 and 32 Kw x 31) 2 Am29PDL129H November 2, 2005 TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Simultaneous Operation Block Diagram . . . . . . . 6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10 Table 1. Am29PDL129H Device Bus Operations ...........................10 PPB Lock Bit Status .............................................................. 27 Table 14. Memory Array Command Definitions ............................. 28 Table 15. Sector Protection Command Definitions ........................ 29 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 30 Figure 6. Maximum Negative Overshoot Waveform ...................... 30 Figure 7. Maximum Positive Overshoot Waveform........................ 30 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. Test Setup, VIO = 2.7 - 3.6 V........................................ 32 Figure 9. Input Waveforms and Measurement Levels ................... 32 Random Read (Non-Page Read) ........................................... 10 Page Mode Read .................................................................... 10 Table 2. Page Select .......................................................................10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33 CE1#/CE2# Timing ................................................................. 33 Figure 10. Timing Diagram for Alternating Between CE1# and CE2# Control............................................................................................ 33 Simultaneous Operation ......................................................... 10 Table 3. Bank Select .......................................................................11 Table 4. Am29PDL129H Sector Architecture ..................................12 Table 5. Addresses .......................................................................19 Table 6. Autoselect Codes (High Voltage Method) ........................19 Table 7. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE1# Control ...................................................................................20 Table 8. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE2# Control ...................................................................................20 Table 9. Sector Protection Schemes ...............................................21 Read-Only Operations ........................................................... 33 Figure 11. Read Operation Timings ............................................... 34 Figure 12. Page Read Operation Timings...................................... 34 Hardware Reset (RESET#) .................................................... 35 Figure 13. Reset Timings ............................................................... 35 Erase and Program Operations .............................................. 36 Figure 14. Program Operation Timings.......................................... Figure 15. Accelerated Program Timing Diagram.......................... Figure 16. Chip/Sector Erase Operation Timings .......................... Figure 17. Back-to-back Read/Write Cycle Timings ...................... Figure 18. Data# Polling Timings (During Embedded Algorithms). Figure 19. Toggle Bit Timings (During Embedded Algorithms)...... Figure 20. DQ2 vs. DQ6................................................................. 37 37 38 39 39 40 40 Write Protect (WP#) ................................................................ 21 Persistent Protection Bit Lock ................................................. 21 High Voltage Sector Protection .............................................. 21 Figure 1. ......................................................................................... 21 Temporary Sector Unprotect .................................................. 41 Figure 21. Temporary Sector Unprotect Timing Diagram .............. 41 Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram 42 Temporary Sector Unprotect .................................................. 21 Figure 2. ......................................................................................... 21 Flash Memory Region ............................................................ 21 Factory-Locked Area (64 words) ............................................ 21 Customer-Lockable Area (64 words) ...................................... 22 Figure 3. SecSi Sector Protection Algorithm................................... 23 Alternate CE# Controlled Erase and Program Operations ..... 43 Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 44 SecSi Sector Protection Bits ................................................... 24 Figure 4. SecSi Sector Protect Verify.............................................. 24 Common Flash Memory Interface (CFI) . . . . . . . 24 Command Definitions . . . . . . . . . . . . . . . . . . . . . 27 Enter /Exit Command Sequence ............................................ 27 Figure 5. ......................................................................................... 27 Erase And Programming Performance. . . . . . . . Latchup Characteristics . . . . . . . . . . . . . . . . . . . . BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 45 45 45 45 46 November 2, 2005 Am29PDL129H 3 PRODUCT SELECTOR GUIDE Part Number Speed Option VCC, VIO = 2.7-3.6 V VCC = 2.7-3.6 V, VIO = 1.65-1.95 V Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max Page Access, ns (tPACC) Max OE# Access, ns (tOE) 55 65 60 20 25 70 30 30 53 Am29PDL129H 63 68 65 85 88 BLOCK DIAGRAM DQ15-DQ0 RY/BY# (See Note) VCC VSS Sector Switches VIO RESET# Erase Voltage Generator WE# State Control Command Register CE1# CE2# OE# PGM Voltage Generator Input/Output Buffers Chip Enable Output Enable Logic Data Latch Y-Decoder VCC Detector Timer Address Latch Y-Gating A21-A3 X-Decoder Cell Matrix A2-A0 Note:RY/BY# is an open drain output. 4 Am29PDL129H November 2, 2005 SIMULTANEOUS OPERATION BLOCK DIAGRAM VCC VSS CE1#=L CE2#=H Mux A21-A0 Bank 1A Address OE# Bank 1A Y-gate X-Decoder A21-A0 RY/BY# Bank 1B Address Bank 1B X-Decoder A21-A0 RESET# WE# CE1# CE2# WP#/ACC STATE CONTROL & COMMAND REGISTER CE1#=H CE2#=L DQ0-DQ15 X-Decoder Status DQ15-DQ0 DQ15-DQ0 DQ15-DQ0 Control Mux A21-A0 X-Decoder A21-A0 Mux Bank 2B Address Bank 2B November 2, 2005 Am29PDL129H DQ15-DQ0 Bank 2A Address Bank 2A Y-gate DQ15-DQ0 5 CONNECTION DIAGRAMS 80-Ball Fine-pitch BGA Top View, Balls Facing Down A8 NC A7 NC B8 NC B7 NC C8 NC C7 A13 C6 A9 C5 WE# C4 D8 NC D7 A12 D6 A8 D5 RESET# D4 E8 NC E7 A14 E6 A10 E5 A21 E4 A18 E3 A6 E2 A2 E1 NC F8 VIO F7 A15 F6 A11 F5 A19 F4 A20 F3 A5 F2 A1 F1 NC G8 VSS G7 A16 G6 DQ7 G5 DQ5 G4 DQ2 G3 DQ0 G2 A0 G1 CE2# H8 NC H7 NC H6 DQ14 H5 DQ12 H4 DQ10 H3 DQ8 H2 CE1# H1 VIO J8 NC J7 DQ15 J6 DQ13 J5 VCC J4 DQ11 J3 DQ9 J2 OE# J1 NC K8 NC K7 VSS K6 DQ6 K5 DQ4 K4 DQ3 K3 DQ1 K2 VSS K1 NC L8 NC L7 NC M8 NC M7 NC RY/BY# WP#/ACC C3 A7 A2 NC A1 NC B2 NC B1 NC C2 A3 C1 NC D3 A17 D2 A4 D1 NC L2 NC L1 NC M2 NC M1 NC Note: On S29PL129J, G1= NC and J1= CE2# 6 Am29PDL129H November 2, 2005 PIN DESCRIPTION A21-A0 = 22-bit address bus for 2 x 64 Mb device. A9 supports 12 V autoselect inputs. 16-bit data inputs/outputs/float Chip Enable Inputs. CE1# controls the 64 Mb in Banks 1A and 1B. CE2# controls the 64 Mb in Banks 2A and 2B. Output Enable Input Write Enable Device Ground Pin Not Connected Internally Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, VIO VCC RESET# = = = WP#/ACC = the device is either executing an embedded algorithm or the device is executing a hardware reset operation. Write Protect/Acceleration Input. When WP/ACC#= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ ACC#= 12V, program and erase operations are accelerated. Input/Output Buffer Power Supply (1.65 V to 1.95 V or 2.7 V to 3.6 V) Chip Power Supply (2.7 V to 3.6 V) Hardware Reset Pin DQ15-DQ0 = CE1#, CE2# = OE# WE# VSS NC RY/BY# = = = = = LOGIC SYMBOL 22 A21-A0 DQ15-DQ0 CE1# CE2# OE# WE# WP#/ACC RESET# RY/BY# 16 VIO (VCCQ) November 2, 2005 Am29PDL129H 7 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29PDL129 H 53 VK I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (-40C to +85C) PACKAGE TYPE VK = 80-Ball Fine-pitch Ball Grid Array 0.8 mm pitch, 11.5 x 9 mm package (VBB080) SPEED OPTION See Product Selector Guide and Valid Combinations PROCESS TECHNOLOGY H = 0.13 m DEVICE NUMBER/DESCRIPTION Am29PDL129H 128 Megabit (8 M x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase Dual Chip Enable Inputs Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations for BGA Packages Order Number Package Marking Speed (ns) VIO Range Note: For the Am29PDL129H, the last digit of the speed grade specifies the VIO range of the device. Speed grades ending in 3 (for example: 53, 63) indicate a 3 Volt VIO range. Speed grades ending in 8 (for example: 68, 88) indicate a 1.8 Volt VIO range. Contact AMD or Fujitsu for availability of 1.8V VIO range devices. Am29PDL129H53 Am29PDL129H63 Am29PDL129H68 Am29PDL129H88 VKI PD129H53V PD129H63V PD129H68V PD129H88V I 55 65 65 85 2.7-3.6 V 2.7-3.6 V 1.65-1.95 V 1.65-1.95 V 8 Am29PDL129H November 2, 2005 DEVICE BUS OPERATIONS Table 1. Operation Read H L Write H Standby Output Disable Reset Temporary Sector Unprotect (High Voltage) VIO 0.3 V L X X L VIO 0.3 V L X X X H X X X H X X VIO 0.3 V H L VID L H H L H X (Note 2) X X X X CE1# L Am29PDL129H Device Bus Operations CE2# H L H H X AIN DOUT OE# WE# RESET# WP#/ACC Addresses (A21-A0) DQ15- DQ0 AIN DIN X X X AIN High-Z High-Z High-Z DIN Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 8.5-9.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment. . 2. WP#/ACC must be high when writing to sectors SA1-133, SA1-134, SA2-0, or SA2-1. Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC-tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits A21- A3 select an 8-word page, and address bits A2-A0 select a specific work within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor fall within that page) are t PACC. When CE1# and CE2# are deasserted (CE1#=CE2#=VIH), the reassertion of CE1# or CE2# for subsequent access has access time of tACC or tCE. Here again, CE1#/CE2# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping A21- A3 constant and changing A2 to A0 to select the specific word within that page. Table 2. Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 Page Select A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Simultaneous Operation In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), The bank can be selected by bank addresses (A21-A20) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. November 2, 2005 Am29PDL129H 9 Table 3. Bank Bank 1A Bank 1B CE1# 0 0 Bank Select A21-A20 00, 01, 10 11 Bank 2A Bank 2B 1 1 0 0 00 01, 10, 11 CE2# 1 1 10 Am29PDL129H November 2, 2005 Table 4. Bank Sector SA1-0 SA1-1 SA1-2 SA1-3 SA1-4 SA1-5 SA1-6 SA1-7 SA1-8 SA1-9 SA1-10 SA1-11 SA1-12 SA1-13 SA1-14 SA1-15 SA1-16 SA1-17 Bank 1A SA1-18 SA1-19 SA1-20 SA1-21 SA1-22 SA1-23 SA1-24 SA1-25 SA1-26 SA1-27 SA1-28 SA1-29 SA1-30 SA1-31 SA1-32 SA1-33 SA1-34 SA1-35 SA1-36 SA1-37 CE1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Am29PDL129H Sector Architecture CE2# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21A12) 0000000XXX 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX 0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh November 2, 2005 Am29PDL129H 11 Table 4. Bank Sector SA1-38 SA1-39 SA1-40 SA1-41 SA1-42 SA1-43 SA1-44 SA1-45 SA1-46 SA1-47 SA1-48 SA1-49 SA1-50 SA1-51 SA1-52 SA1-53 SA1-54 SA1-55 SA1-56 Bank 1A SA1-57 SA1-58 SA1-59 SA1-60 SA1-61 SA1-62 SA1-63 SA1-64 SA1-65 SA1-66 SA1-67 SA1-68 SA1-69 SA1-70 SA1-71 SA1-72 SA1-73 SA1-74 SA1-75 SA1-76 SA1-77 CE1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Am29PDL129H Sector Architecture CE2# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21A12) 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 12 Am29PDL129H November 2, 2005 Table 4. Bank Sector SA1-78 SA1-79 SA1-80 SA1-81 SA1-82 SA1-83 SA1-84 SA1-85 Bank 1A SA1-86 SA1-87 SA1-88 SA1-89 SA1-90 SA1-91 SA1-92 SA1-93 SA1-94 SA1-95 CE1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Am29PDL129H Sector Architecture CE2# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21A12) 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh November 2, 2005 Am29PDL129H 13 Table 4. Bank Sector SA1-96 SA1-97 SA1-98 SA1-99 SA1-100 SA1-101 SA1-102 SA1-103 SA1-104 SA1-105 SA1-106 SA1-107 SA1-108 SA1-109 SA1-110 SA1-111 SA1-112 SA1-113 Bank 1B SA1-114 SA1-115 SA1-116 SA1-117 SA1-118 SA1-119 SA1-120 SA1-121 SA1-122 SA1-123 SA1-124 SA1-125 SA1-126 SA1-127 SA1-128 SA1-129 SA1-130 SA1-131 SA1-132 SA1-133 SA1-134 CE1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Am29PDL129H Sector Architecture CE2# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21A12) 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range (x16) 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh 14 Am29PDL129H November 2, 2005 Table 4. Bank Sector SA2-0 SA2-1 SA2-2 SA2-3 SA2-4 SA2-5 SA2-6 SA2-7 SA2-8 SA2-9 SA2-10 SA2-11 SA2-12 SA2-13 SA2-14 SA2-15 SA2-16 SA2-17 Bank 2A SA2-18 SA2-19 SA2-20 SA2-21 SA2-22 SA2-23 SA2-24 SA2-25 SA2-26 SA2-27 SA2-28 SA2-29 SA2-30 SA2-31 SA2-32 SA2-33 SA2-34 SA2-35 SA2-36 SA2-37 SA2-38 CE1# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Am29PDL129H Sector Architecture CE2# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21A12) 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh November 2, 2005 Am29PDL129H 15 Table 4. Bank Sector SA2-39 SA2-40 SA2-41 SA2-42 SA2-43 SA2-44 SA2-45 SA2-46 SA2-47 SA2-48 SA2-49 SA2-50 SA2-51 SA2-52 SA2-53 SA2-54 SA2-55 SA2-56 SA2-57 Bank 2B SA2-58 SA2-59 SA2-60 SA2-61 SA2-62 SA2-63 SA2-64 SA2-65 SA2-66 SA2-67 SA2-68 SA2-69 SA2-70 SA2-71 SA2-72 SA2-73 SA2-74 SA2-75 SA2-76 SA2-77 SA2-78 CE1# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Am29PDL129H Sector Architecture CE2# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21A12) 0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 16 Am29PDL129H November 2, 2005 Table 4. Bank Sector SA2-79 SA2-80 SA2-81 SA2-82 SA2-83 SA2-84 SA2-85 SA2-86 SA2-87 SA2-88 SA2-89 SA2-90 SA2-91 SA2-92 SA2-93 SA2-94 SA2-95 SA2-96 SA2-97 Bank 2B SA2-98 SA2-99 SA2-100 SA2-101 SA2-102 SA2-103 SA2-104 SA2-105 SA2-106 SA2-107 SA2-108 SA2-109 SA2-110 SA2-111 SA2-112 SA2-113 SA2-114 SA2-115 SA2-116 SA2-117 SA2-118 CE1# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Am29PDL129H Sector Architecture CE2# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21A12) 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh November 2, 2005 Am29PDL129H 17 Table 4. Bank Sector SA2-119 SA2-120 SA2-121 SA2-122 SA2-123 SA2-124 SA2-125 Bank 2B Am29PDL129H Sector Architecture CE2# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21A12) 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh CE1# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA2-126 SA2-127 SA2-128 SA2-129 SA2-130 SA2-131 SA2-132 SA2-133 SA2-134 Table 5. Am29PDL129H Factory-Locked Area Customer-Lockable Area Addresses Address Range 000000h-00007Fh 000000h-00003Fh 000040h-00007Fh 128 words 64 words 64 words Sector Size Table 6. Autoselect Codes (High Voltage Method) A21 to A12 X A5 to A4 X DQ15 to DQ0 0001h Description Manufacturer ID: AMD Read Cycle 1 Device ID Read Cycle 2 Read Cycle 3 Sector Protection Verification CE1# L H L H L H L H L H L CE2# H OE# L WE# H A10 X A9 VID A8 X A7 L A6 L A3 L A2 L A1 L A0 L L H L L H L L H H L H L L H L H X X VID X X L X L L H H L H SA X VID X L L L L L H L 0001h (protected), 0000h (unprotected) 00C0h (factory and customer locked), 0080h (factory locked) H H H 2200h H X X VID X L L L H H H L 2221h L L H 227Eh Indicator Bit (DQ7, DQ6) H Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don't care. Note: The autoselect codes may also be accessed in-system via command sequences Table 7. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE1# Control Sector Group SA1-0-SA1-3 A21-12 00000XXXXX Sector/Sector Block Size 128 (4x32) Kwords 18 Am29PDL129H November 2, 2005 Sector Group SA1-4-SA1-7 SA1-8-SA1-11 SA1-12-SA1-15 SA1-16-SA1-19 SA1-20-SA1-23 SA1-24-SA1-27 SA1-28-SA1-31 SA1-32-SA1-35 SA1-36-SA1-39 SA1-40-SA1-43 SA1-44-SA1-47 SA1-48-SA1-51 SA1-52-SA1-55 SA1-56-SA1-59 SA1-60-SA1-63 SA1-64-SA1-67 SA1-68-SA1-71 SA1-72-SA1-75 SA1-76-SA1-79 SA1-80-SA1-83 SA1-84-SA1-87 SA1-88-SA1-91 SA1-92-SA1-95 SA1-96-SA1-99 SA1-100-SA1-103 SA1-104-SA1-107 SA1-108-SA1-111 SA1-112-SA1-115 SA1-116-SA1-119 SA1-120-SA1-123 SA1-124 SA1-125 SA1-126 SA1-127 SA1-128 SA1-129 SA1-130 SA1-131 SA1-132 SA1-133 SA1-134 A21-12 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector/Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords Table 8. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE2# Control Sector Group SA2-0 SA2-1 SA2-2 SA2-3 SA2-4 SA2-5 SA2-6 SA2-7 SA2-8 SA2-9 SA2-10 SA2-11 - SA2-14 SA2-15 - SA2-18 SA2-19 - SA2-22 SA2-23 - SA2-26 SA2-27 - SA2-30 SA2-31 - SA2-34 SA2-35 - SA2-38 SA2-39 - SA2-42 SA2-43 - SA2-46 SA2-47 - SA2-50 SA2-51 - SA2-54 SA2-55 - SA2-58 SA2-59 - SA2-62 SA2-63 - SA2-66 SA2-67 - SA2-70 SA2-71 - SA2-74 SA2-75 - SA2-78 SA2-79 - SA2-82 SA2-83 - SA2-86 SA2-87 - SA2-90 SA2-91 - SA2-94 SA2-95 - SA2-98 SA2-99 - SA2-102 SA2-103 - SA2-106 SA2-107 - SA2-110 SA2-111 - SA2-114 SA2-115 - SA2-118 SA2-119 - SA2-122 SA2-123 - SA2-126 SA2-127 - SA2-130 SA2-131 - SA2-134 A21-12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 11111XXXXX Sector/Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords November 2, 2005 Am29PDL129H 19 Selecting a Sector Protection Mode The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details. Table 9. Sector Protection Schemes Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting sectors without using VID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in High Voltage Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. High Voltage Sector Protection Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. Figure 1. Temporary Sector Unprotect Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors will remain protected). 2. All previously protected sectors are protected once again. indicator bits (DQ6, DQ7) to indicate the factorylocked and customer-locked status of the part. The system accesses the through a command sequence (see "Enter /Exit Command Sequence"). After the system has written the Enter command sequence, it may read the by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Factory-Locked Area (64 words) The factory-locked area of the SecSi Sector (000000h00003Fh) is locked when the part is shipped, whether or not the area was programmed at the factory. The SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a "1". AMD offers the ExpressFlash service to program the factory-locked area with a random ESN, a customer-defined code, or any combina- Figure 2. Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The SecSi sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. It uses 20 Am29PDL129H November 2, 2005 tion of the two. Because only AMD can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact an AMD representative for details on using AMD's ExpressFlash service. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Customer-Lockable Area (64 words) The customer-lockable area of the SecSi Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The SecSi Sector Customer-locked Indicator Bit (DQ6) is shipped as "0" and can be permanently locked to "1" by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The Customer-lockable area can be protected using one of the following procedures: Follow the SecSi Sector Protection Algorithm as shown in . This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. November 2, 2005 Am29PDL129H 21 START SecSiTM Sector Entry Write AAh to address 555h Write 55h to address 2AAh Write 88h to address 555h SecSi Sector Protection Entry Write AAh to address 555h Write 55h to address 2AAh Write 60h to address 555h PLSCNT = 1 Protect SecSi Sector: write 68h to sector address with A7-A0 = 00011010 Time out 256 s Verify SecSi Sector: write 48h to sector address with A7-A0 = 00011010 Read from sector address with A7-A0 = 00011010 No Data = 01h? Yes SecSi Sector Protection Completed SecSi Sector Exit Write 555h/AAh Write 2AAh/55h Write SA0+555h/90h Write XXXh/00h Figure 3. SecSi Sector Protection Algorithm To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 4. 22 Am29PDL129H November 2, 2005 Once the is locked and verified, the system must write the Exit Region command sequence to return to reading and writing the remainder of the array. The must be used with caution since, once locked, there is no procedure available for unlocking the area and none of the bits in the memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable. START RESET# = VIH or VID Wait 1 s Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Write reset command SecSi Sector Protect Verify complete Figure 4. SecSi Sector Protect Verify COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 10-13. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 10-13. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. Table 10. Addresses Data CFI Query Identification String Description November 2, 2005 Am29PDL129H 23 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 11. Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0004h 0000h 0009h 0000h 0005h 0000h 0004h 0000h System Interface String Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) Table 12. Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h Data 0018h 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h Device Geometry Definition Description Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) 24 Am29PDL129H November 2, 2005 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) November 2, 2005 Am29PDL129H 25 Table 13. Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 000Ch Primary Vendor-Specific Extended Query Description Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 0002h 0001h 0001h 0007h 00E7h 0000h 0002h 0085h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 4Eh 0095h 4Fh 0001h 00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 50h 0001h 57h 0004h 58h 0027h 59h 0060h 5Ah 0060h 5Bh 0027h 26 Am29PDL129H November 2, 2005 COMMAND DEFINITIONS Enter /Exit Command Sequence The region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the region by issuing the three-cycle Enter command sequence. The device continues to access the region until the system issues the four-cycle Exit command sequence. The Exit ommand sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. shows the address and data requirements for both command sequences. See also "SecSi Sector Flash Memory Region and Enter SecSi Sector/Exit SecSi Sector Command Sequence" for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Figure 5. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. If the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. PPB Lock Bit Status Sector Protection Status The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group. November 2, 2005 Am29PDL129H 27 Command Definitions Tables Table 14. Command (Notes) Read (5) Reset (6) Manufacturer ID Device ID (10) Autoselect (Note 7) SecSi Sector Factory Protect (8) Sector Group Protect Verify (9) Program Chip Erase Sector Erase Program/Erase Suspend (11) Program/Erase Resume (12) CFI Query (13) Accelerated Program (15) Unlock Bypass Entry (15) Unlock Bypass Program (15) Unlock Bypass Erase (15) Unlock Bypass CFI (13, 15) Unlock Bypass Reset (15) Cycles Memory Array Command Definitions Bus Cycles (Notes 1-4) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data RA XXX 555 555 555 555 555 555 555 BA BA 55 XX 555 XX XX XX XXX RD F0 AA AA AA AAA AA AA AA B0 30 98 A0 AA A0 80 98 90 XXX 00 PA 2AA PA XX PD 55 PD 10 555 20 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 555 555 555 555 555 555 555 90 90 90 90 A0 80 80 1 1 4 6 4 4 4 6 6 1 1 1 2 3 2 2 1 2 (BA)X00 (BA)X01 X03 (SA)X02 PA 555 555 01 7E (see note 8) XX00/ XX01 PD AA AA 2AA 2AA 55 55 555 SA 10 30 (BA)X0E 21 (BA)X0F 00 Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by A21:A20, see Tables 4 and for more detail. PA = Program Address (A21:A0). Addresses latch on falling edge of WE# or CE1#/CE2# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE1#/CE2# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. 3. 4. All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See Autoselect Command Sequence for more information. RA = Read Address (A21:A0). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A21:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See "Configuration Register" definition for specific write data. Data latched on rising edge of WE#. X = Don't care 8. 9. The data is C0h for factory or customer locked and 80h for factory locked. The data is 00h for an unprotected sector group and 01h for a protected sector group. 10. Device ID must be read across cycles 4, 5, and 6. 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. must be at VID during the entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array. 5. 6. 7. 28 Am29PDL129H November 2, 2005 Table 15. Command (Notes) Reset SecSi Sector Exit SecSi Protection Bit Program (5, 6) SecSi Protection Bit Status Cycles Addr Data Addr Data F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 Addr Sector Protection Command Definitions Bus Cycles (Notes 1-4) Data Addr Data Addr Data Addr Data Addr Data 1 XXX 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 4 6 5 SecSi Sector Entry 3 88 90 60 60 38 C8 28 60 60 60 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 48 68 48 PL PL SL SL 48 RD(0) 48 RD(0) SL RD(0) PL RD(0) XX OW OW XX[0-3] PWA[0-3] PWA[0] (SA)WP (SA)WP WP 00 68 48 PD[0-3] PWD[0-3] PWD[0] 68 48 60 PWA[1] (SA)WP (SA)WP (SA) PWD[1] 48 RD (0) 40 (SA)WP RD(0) PWA[2] (SA)WP PWD[2] RD(0) PWA[3] PWD[3] OW OW 48 RD(0) OW RD(0) Password Program 4 (5, 7, 8) Password Verify (6, 4 8, 9) Password Unlock (7, 10, 11) 7 PPB Program (5, 6, 6 12, 17) PPB Status All PPB Erase (5, 6, 13, 14) PPB Lock Bit Set (17) PPB Lock Bit Status (15) DYB Write (7) DYB Erase (7) PPMLB Program (5, 6, 12) PPMLB Status (5) SPMLB Program (5, 6, 12) SPMLB Status (5) 5 6 3 4 4 4 DYB Status (6, 18) 4 6 5 6 5 Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit. 1. See Table 1 for description of bus operations. RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits A21:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) (Note16) X = Don't care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 11. A 2 s timeout is required between any two portions of password. 12. A 100 s timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. 16. For PDL128G and PDL640G, the WP address is 0111010. The EP address (PPB Erase Address) is 1111010. 17. Following the final cycle of the command sequence, the user must write the first three cycles of the Autoselect command and then write a Reset command. 18. If checking the DYB status of sectors in multiple banks, the user must follow Note 17 before crossing a bank boundary. 2. 3. 4. All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. The reset command returns device to reading array. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. Data is latched on the rising edge of WE#. Entire command sequence must be entered for each portion of password. Command sequence returns FFh if PPMLB is set. 5. 6. 7. 8. 9. 10. The password is written over four consecutive cycles, at addresses 0-3. November 2, 2005 Am29PDL129H 29 ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . -0.5 V to +13.0 V (Note 2) . . . . . . . . . . . . . . . . . . . -0.5 V to +10.5 V All other pins (Note 1) . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See . During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 7. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is -0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to - 2.0 V for periods of up to 20 ns. See . Maximum DC input voltage on pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns Figure 6. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns Figure 7. Maximum Positive Overshoot Waveform OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7-3.6 V VIO (see Note) . . . . . . . . . . .1.65-1.95 V or 2.7-3.6 V For all AC and DC specifications, VIO = VCC; contact AMD for other VIO options. Operating ranges define those limits between which the functionality of the device is guaranteed. 30 Am29PDL129H November 2, 2005 DC CHARACTERISTICS CMOS Compatible Parameter Symbol ILI ILIT ILR ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 VIL Parameter Description Input Load Current A9, OE#, RESET# Input Load Current Reset Leakage Current Output Leakage Current VCC Active Read Current (Notes 1, 2, 3) VCC Active Write Current (Notes 1, 3, 4) VCC Standby Current (Note 3) VCC Reset Current (Note 3) Automatic Sleep Mode (Notes 3, 5) VCC Active Read-While-Program Current (Notes 1, 2, 3) VCC Active Read-While-Erase Current (Notes 1, 2, 3) VCC Active Program-While-EraseSuspended Current (Notes 1, 3, 6) Input Low Voltage Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; VID= 12.5 V VCC = VCC max; VID= 12.5 V VOUT = VSS to VCC, OE# = VIH VCC = VCC max OE# = VIH, VCC = VCC max (Note 1) OE# = VIH, WE# = VIL CE1#, CE2#, RESET#, WP/ACC# = VIO 0.3 V RESET# = VSS 0.3 V, CE# = VSS VIH = VIO 0.3 V; VIL = VSS 0.3 V, CE# = VSS OE# = VIH OE# = VIH OE# = VIH VIO = 1.65-1.95 V VIO = 2.7-3.6 V VIO = 1.65-1.95 V VIO = 2.7-3.6 V Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage VCC = 3.0 V 10% VCC = 3.0 V 10% IOL = 100 A, VCC = VCC min, VIO = 1.65-1.95 V IOL = 2.0 mA, VCC = VCC min, VIO = 2.7-3.6 V VOH VLKO Output High Voltage Low VCC Lock-Out Voltage (Note 6) 4. 5. IOH = -100 A, VCC = VCC min, VIO = 1.65-1.95 V Min Typ Max 1.0 35 35 1.0 Unit A A A A mA mA A A A mA mA mA V V V V V V V V V V 5 MHz 10 MHz 20 45 15 1 1 1 30 55 25 5 5 5 45 45 25 0.4 0.8 VIO+0.4 VCC+0.3 9.5 12.5 0.1 0.4 Word Word 21 21 17 -0.4 -0.5 VIO-0.4 2.0 8.5 11.5 VIH VHH VID Input High Voltage VOL VIO-0.1 2.4 2.3 2.5 IOH = -2.0 mA, VCC = VCC min, VIO = 2.7-3.6 V V Notes: 1. Valid CE1#/CE2# conditions: (CE1#= VIL, CE2#= VIH) or (CE1#= VIH, CE2#= VIL) 2. 3. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. Maximum ICC specifications are tested with VCC = VCCmax. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 150 ns. Typical sleep mode current is 1 A. Not 100% tested. 6. November 2, 2005 Am29PDL129H 31 TEST CONDITIONS Table 16. 3.6 V Test Condition 2.7 k Output Load Output Load Capacitance, CL (including jig capacitance) CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Specifications All Speeds 1 TTL gate 30 5 0.0-3.0 1.5 1.5 pF ns V V V Unit Device Under Test Note: Diodes are IN3064 or equivalent Figure 8. Test Setup, VIO = 2.7 - 3.6 V Note: For 70 pF output load capacitance, 2 ns will be added to certain read-only operation parameters. * For VIO = 1.65 - 1.95 Test Setup, the device is tested using CL only KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS VIO 0.0 V Input VIO/2 Measurement Level VIO/2 Output Figure 9. Input Waveforms and Measurement Levels 32 Am29PDL129H November 2, 2005 AC CHARACTERISTICS CE1#/CE2# Timing Parameter JEDEC Std tCCR Description CE1#/CE2# Recover Time Min All Speed Options 30 Unit ns CE1# tCCR CE2# tCCR Figure 10. Timing Diagram for Alternating Between CE1# and CE2# Control Read-Only Operations Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE Description Read Cycle Time (Note 1) Address to Output Delay (Note 3) Chip Enable to Output Delay (Note 4) CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min 53 55 55 60 20 20 Speed Options 63 65 65 65 25 25 16 16 5 0 10 68 65 65 70 30 30 88 85 85 85 Unit ns ns ns ns ns ns ns ns ns ns tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output High Z (Notes 1, 5, 6) Output Enable to Output High Z (Notes 1, 5) Output Hold Time From Addresses, CE#/CE2# or OE#, Whichever Occurs First (Notes 5, 6) Read tOEH Notes: 1. Not 100% tested. Output Enable Hold Time (Note 1) Toggle and Data# Polling 5. 2. 3. 4. See Figure 8 and Table 16 for test specifications Valid CE1#/CE2# conditions: (CE1#= VIL, CE2#= VIH) or (CE1#= VIH, CE2#=VIL). Valid CE1#/CE2# transitions: (CE1#= CE2#= VIH) to (CE1#= VIL, CE2#=VIH) or (CE1#= VIH, CE2#=VIL). 6. 7. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. Valid CE1#/CE2# transitions: (CE1#= VIL, CE2#= VIH) or (CE1#= VIH, CE2#=VIL) to (CE1#= CE2#= VIH). For 70 pF output load capacitance, 2 ns will be added to tACC, tCE, tPACC, tOE values for all speed options. November 2, 2005 Am29PDL129H 33 AC CHARACTERISTICS tRC Addresses CE1# or CE2# tRH tRH OE# tOEH WE# HIGH Z Data RESET# RY/BY# Valid Data tCE tOH HIGH Z tOE tDF Addresses Stable tACC 0V Figure 11. Read Operation Timings Note: 1. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH Addresses Same Page A2-A0 Aa tACC Ab tPACC Ac tPACC tPACC Ad Data CE1# or CE2# OE# Figure 12. Qa Qb Qc Qd Page Read Operation Timings Note: 1. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH 34 Am29PDL129H November 2, 2005 AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit s ns ns ns s ns Note: Not 100% tested. RY/BY# CE1# or CE2#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE1# or CE2#, OE# RESET# tRP Figure 13. Reset Timings Note: 1. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH November 2, 2005 Am29PDL129H 35 AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE1#, CE2#, or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE1# or CE2# Setup Time CE1# or CE2# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max 35 20 0 6 4 0.5 50 0 90 25 0 10 0 0 0 40 25 30 0 30 53 55 Speed Options 63 65 0 15 35 68 65 88 85 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s sec s ns ns tWHWH1 Programming Operation (Note 2) tWHWH1 Accelerated Programming Operation (Note 2) tWHWH2 Sector Erase Operation (Note 2) tVCS tRB tBUSY VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 36 Am29PDL129H November 2, 2005 AC CHARACTERISTICS Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE1# or CE2# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles) tCH A0h VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH Figure 14. Program Operation Timings VHH WP#/ACC VIL or VIH tVHH tVHH VIL or VIH Figure 15. Accelerated Program Timing Diagram November 2, 2005 Am29PDL129H 37 AC CHARACTERISTICS Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase Read Status Data VA tAH VA CE1# or CE2# OE# tWP WE# tCS tDS tCH tWPH tWHWH2 tDH Data 55h 30h 10 for Chip Erase Status DOUT tBUSY RY/BY# tVCS VCC tRB Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (.) 2. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH Figure 16. Chip/Sector Erase Operation Timings 38 Am29PDL129H November 2, 2005 AC CHARACTERISTICS tWC Addresses tAS CE1# or CE2# Valid PA tRC Valid RA tWC Valid PA tWC Valid PA tAH tACC tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data Valid In tAS tCPH tAH tCP tGHWL tDF tOH Valid Out Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles Note: 1. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH Figure 17. Back-to-back Read/Write Cycle Timings tRC Addresses VA tACC tCE CE1# or CE2# tCH OE# tOEH WE# tOH DQ7 High Z VA VA tOE tDF Complement Complement True Valid Data High Z DQ6-DQ0 tBUSY RY/BY# Status Data Status Data True Valid Data Note: 1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. During CE1# transitions, CE2#= VIH; 2. During CE2# transitions, CE1#= VIH Figure 18. Data# Polling Timings (During Embedded Algorithms) November 2, 2005 Am29PDL129H 39 AC CHARACTERISTICS tAHT Addresses tAHT tASO CE1# or CE2# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data Valid Status tAS tCEPH tOE Valid Status Valid Status Valid Data (first read) RY/BY# (second read) (stops toggling) Notes: 1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 2. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH Figure 19. Toggle Bit Timings (During Embedded Algorithms) Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: 1. DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 20. DQ2 vs. DQ6 40 Am29PDL129H November 2, 2005 AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns s s Note: Not 100% tested. VID RESET# VIL or VIH tVIDR Program or Erase Command Sequence CE1# or CE2# tVIDR VID VIL or VIH WE# tRSP RY/BY# tRRB Note: During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH Figure 21. Temporary Sector Unprotect Timing Diagram November 2, 2005 Am29PDL129H 41 AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Sector Group Protect/Unprotect Valid* Verify 40h Valid* Data 1 s CE1# or CE2# 60h 60h Status Sector Group Protect: 150 s Sector Group Unprotect: 15 ms WE# OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Notes: 1. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram 42 Am29PDL129H November 2, 2005 AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE1# or CE2# Pulse Width CE1# or CE2# Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation (Note 2) Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 35 20 6 4 0.5 30 25 0 0 0 0 40 25 53 55 Speed Options 63 65 0 35 30 68 65 88 85 Unit ns ns ns ns ns ns ns ns ns ns s s sec Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. November 2, 2005 Am29PDL129H 43 AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE1# or CE2# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. 2. 3. 4. Figure indicates last two bus cycles of a program or erase operation. PA = program address, SA = sector address, PD = program data. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. During CE1# transitions, CE2#= VIH; During CE2# transitions, CE1#= VIH Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings 44 Am29PDL129H November 2, 2005 ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Typ (Note 1) 0.4 108 6 4 50 210 120 200 Max (Note 2) 5 Unit sec sec s s sec Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 13 V VCC + 1.0 V +100 mA Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time, VIO = VCC BGA BALL CAPACITANCE Parameter Symbol CIN COUT CIN2 Notes: 1. 2. Sampled, not 100% tested. Test conditions TA = 25C, f = 1.0 MHz. Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 4.2 5.4 3.9 Max 5.0 6.5 4.7 Unit pF pF pF DATA RETENTION Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years November 2, 2005 Am29PDL129H 45 REVISION SUMMARY Revision A (September 30, 2002) Initial release. Sector Erase Command Sequence and Chip Erase Command Sequence Added "" Table 14. "Memory Array Command Definitions Revision A+1 (October 30, 2002) Product Selector Guide Modified format of product selector guide table. Ordering Information Changed TBD to VK under the package type classification. Added VK packages to Valid Combinations table. Changed the first address of the unlock bypass reset command sequence from BA to XXX. CMOS Compatible Added ILR parameter to table. Deleted IACC parameter from table. Revision A+2 (January 24, 2003) Ordering Information Corrected the ordering part number and package markings for the 83 and 88 speed options. Global Changed 55 speed option to 53, changed 65 speed option to 63 and 68. Table 1. Am29PDL127H Device Bus Operations Added note #2. Requirements for Reading Array Data Reworded Page Mode Read section Common Flash Memory Interface (CFI) Changed wording in last sentence of third paragraph from, "...the autoselect mode." to "...reading array data." Changed CFI website address. Command Definitions Changed wording in last sentence of first paragraph from, "...resets the device to reading array data." to ..."may place the device to an unknown state. A reset command is then required to return the device to reading array data." Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and Figure 3. SecSi Sector Flash Memory Region and Enter SecSi Sector/Exit SecSi Sector Command Sequence Added notes, "Note that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled." Revision A+3 (February 26, 2003) Table 16. Test Specifications Updated output load capacitance. Revision A + 4 (April 22, 2003) Inserted and revised cross references. Revision A+5 (June 20, 2003) Distinctive Characteristics Changed the active read current to 55 mA. Product Selector Guide Added row to table to expand speed options and allow for another VCC range. Physical Dimensions Removed the LAA064 package. Revision B (July 29, 2003) Global Changed most CE# references to CE1#. Changed Bank C to Bank 1A, Bank D to Bank 1B, Bank A to Bank 2A, and Bank B to Bank 2B. Sector Configuration Table Corrected CE1# and CE2# bank references. Table 4. Am29PDL129H Sector Architecture Changed the Bank order to 1A, 1B, 2A, and 2B. 46 Am29PDL129H November 2, 2005 Table 7. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection Broke table up into CE1# and CE2# versions and made modifications to table values to reflect change. WP# Hardware Protection Indicated that a write protect pin that can prevent program or erase operations in sectors SA1-133, SA1134, SA2-0 and SA2-1. Table 15. Sector Protection Command Definitions Corrected typos in the PPB status row. Added Note 17 to PPB Program and PPB Lock Bit Set commands. Added Note 18 to DYB Status. Test Conditions Added note to Figure 10. Table 16. Test Specifications Added specific speed options to table. CMOS Compatible Table Added CE# = VSS to ICC4 and ICC5. Figure 11. Input Waveforms and Measurement Levels Modified values to read VCC. mA; changed program/erase current from 25 to 15 mA. Connection Diagrams Corrected signal descriptions for balls G1 and J1 on 80-ball fine-pitch BGA package (VBB080). DC Characteristics Changed IOL test conditions for VOL from 4.0 mA to 2.0 mA. Table 16, Test Specifications Changed CL from 70 pF to 30 pF. Added note for 70 pF load capacitance. AC Characteristics Read-only Operations table: Added note for 70 pF load capacitance. SecSiTM (Secured Silicon) Sector Flash Memory Region Customer-Lockable Area: Added sector protection figure and changed figure reference in this section from Figure 1 to Figure 3. Table 16. Sector Protection Command Definitions Corrected number of cycles for SecSi Protection Bit Status, PPMLB Status, and SPMLB Status from 4 to 5 cycles. For these command sequences, inserted a cycle before the final read cycle (RD0). Revision B+1 (August 8, 2003) Ordering Information Corrected typo in package marking. Revision B+3 (November 2, 2005) Updated migration statement on cover page and first page of data sheet. This product has been retired and is not available for designs. For new and current designs, Am29PDL129J supersedes Am29PDL129H and is the factory-recomm e n d e d m i g r a t i o n p a t h . P l e a s e r e fe r t o t h e Am29PDL129J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Updated trademarks. Revision B+2 (December 5, 2003) Global Deleted the 83 speed option (85 ns tACC, VIO = 2.7- 3.6V). Replaced the 88 speed option (85 ns tACC, VIO = 1.65-1.95V) with 78 (70 ns tACC, VIO = 1.65-1.95V). Distinctive Characteristics Performance Characteristics: Under Power Consumption bullet, changed active read current from 55 to 45 Trademarks Copyright (c) 2000-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. November 2, 2005 Am29PDL129H 47 |
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